It is commonplace in the sciences to require the generation of an electrical signal having certain specified characteristics, among them frequency, amplitude, and waveshape. Frequency synthesis is a broad term for the art of generating a signal whose frequency is a rational number times the frequency of an available reference or clock source. This number can be varied by a user to produce many choices of the frequency of the generated signal. The resolution of a frequency synthesizer refers to the minimum frequency difference between allowable choices.
Common techniques established in the synthesis art include
a) direct synthesis: combining various harmonics and subharmonics of the reference source; PA1 b) indirect synthesis: using a phase lock loop to regulate a tunable oscillator to a harmonic of the reference; PA1 c) direct digital synthesis (DDS): using a reference clock to govern the periodic computing of samples of a chosen signal. When an analog signal is wanted, a D/A converter is used to transform the samples.
DDS is a straightforward concept: at regular time intervals, digital computing apparatus computes the phase of a desired signal. That is, it computes discrete samples of the continually increasing phase 2.pi.ft of a signal of frequency f. Then, for each phase sample, it computes the corresponding magnitude of the signal. The relationship between phase and magnitude is commonly sinusoidal, but many others (e.g., triangular) are possible. General-purpose computational hardware, such as a microprocessor, can be used to compute the desired signal samples. The usual practice, however, is to use specialized hardware called a "phase accumulator" in order to gain speed and efficiency.
A typical phase accumulator circuit is seen in FIG. 1. When a clock signal f.sub.c is applied, an adder 11 adds a constant number K to the contents of an accumulator register 12 and saves the sum in register 12. The sequence of numbers stored in register 12 corresponds to successive samples of the phase 2.pi.ft of a desired signal; the additive constant K, called the phase increment, represents the frequency of the signal. Of course, adder 11 has a finite capacity and it overflows when this is reached. But this limitation is conveniently accomodated by the fact that the desired sinusoidal signal is periodic: the phase argument 2.pi.ft of the sine function is equally valid when replaced by 2.pi.ft modulo 2.pi.. Thus, the number causing overflow of adder 11--its arithmetic modulus--corresponds to 2.pi. radians; that is, one cycle of phase.
If f.sub.c is the clock frequency, K is the phase increment, and D is the arithmetic modulus of the adder, then the circuit of FIG. 1 generates samples of a signal of frequency f, given by ##EQU1##
There is a difficulty in the practical implementation of DDS which derives from the following considerations. Users customarily want to specify the resolution of the frequency f (the minimum difference between choices of f) as a "decimally-defined" number, a term used in this disclosure to denote a number composed of a power of ten times a (relatively) small integer. Likewise, the clock frequency, f.sub.c, is customarily a decimally-defined number. Yet D, the modulus of the adder 11, is usually a power of two, because it is desirable to use binary hardware for registers, adders, and other components for reasons of speed and efficiency. These practical choices lead to a problem of numerical incompatibility, as this example shows:
Let f.sub.c =1 MHz and D=2.sup.16. Then the synthesized frequency f will be a multiple of 10.sup.6 /2.sup.16 =15.268+ Hz. This number is also the resolution and is decidedly not decimally-defined.
The problem of numerical incompatibility among the components of Eq. 1, and some prior efforts to solve it, are discussed more fully in U.S. Pat. No. 4,951,004 issued Aug. 21, 1990 to Sheffer et al. Sheffer also discloses an effective solution to this problem. A nearly identical solution is presented in the Hewlett-Packard Journal of February, 1989, page 68. Both teach how to synthesize, from an available decimally-defined reference, an appropriate clock frequency f.sub.c having sufficient binary factors to cancel those in D, while providing for the desired decimal resolution of f.
Nevertheless, there are difficulties with these solutions. The most obvious is the need for a phase locked loop to synthesize f.sub.c. Building this partially analog circuit requires components which are difficult to include in a large-scale integrated circuit whose other components are digital. In addition, the user may want to change the resolution, requiring a change in f.sub.c. This may mean reconfiguring the loop filter and waiting for the loop to settle.
Another potential problem is that, depending on the choice of the reference frequency and the desired resolution, the required f.sub.c may be uncomfortably high for operating the DDS hardware. In addition, when f.sub.c is different from the main system reference frequency, spurious signals may appear in the desired output, as the Hewlett-Packard reference illustrates.
There remains, therefore, a need to solve the problem of numerical incompatibility using only integratable digital hardware operating at a decimally-defined clock frequency.